To meet the ever-present demand for increased speed and accuracy in analog-to-digital converters (ADCs), techniques such as time-interleaving have become increasingly popular. Referring to FIG. 1, in a time-interleaved ADC 90, multiple component ADCs or sub-ADCs 911-91N are provided to perform analog-to-digital conversion operations in response to a set of phase-staggered clock signals 94. By this operation, multiple analog-to-digital conversions are pipelined, with the outputs of the sub-ADCs 91 becoming valid one after another on an output line 96. Thus, where a single sub-ADC 91 may be capable of providing an M-bit digital representation of the input signal once per clock cycle, the aggregate operation of time-interleaved sub-ADCs 911-91N provides N such digital representations of the input signal per clock cycle and thus N-times faster ADC operation.
Gain mismatch in sub-ADCs 91 and timing offsets in the clock signals 94 used to trigger time-interleaved conversion operations can limit the performance of a time-interleaved ADC, even if the slower sub-ADCs are of sufficient accuracy. Thus, techniques for eliminating or minimizing such gain mismatches and timing offsets can be critical.